1. Field of the Invention
This invention relates to an ion implantation system and an ion implantation method and more particularly to an ion implantation system and an ion implantation method which can select suitably an implantation energy and implantation dose when impurity ions are implanted on a specific region of a semiconductor substrate of a semiconductor device, or of a semiconductor film for forming a semiconductor element on a glass substrate of a FPD (Flat Panel Display) apparatus.
2. Description of the Prior Art
In the manufacture of the semiconductor device or FPD apparatus, there is the process that impurity ions are doped into a specific region of a semiconductor device, or of a semiconductor film for forming a semiconductor element on a glass plate, using an ion implantation system.
An ion lithography technique is usually used for implanting impurity ions on the specified region. Hereafter, “semiconductor substrate” is assumed to include “semiconductor film for forming a semiconductor element”. In the lithographic technique, photo-resist coating, exposure to light, photo-resist development, photo-resist ashing and wet cleaning are required. Those processes are essential in the conventional ion-implantation process. Then, an ion beam is scanned on the whole surface of the semiconductor substrate to implant the impurity ions on the specified regions through the openings of the resist film, and the remaining resist film is removed.
In the above ion beam scanning process, it is required that the ion beam is incident on the whole surface of the semiconductor substrate at the right angle. This requirement causes the distance between the ion source and the semiconductor substrate to be long. When a semiconductor substrate is large sized, such as 300 mmΦ in diameter, an ion implantation system is large-sized and causes the cost to rise. For solving such a problem or for small-sizing the apparatus, the Japanese Patent Opening Gazette No. 288680/1999 discloses the apparatus in which a beam shielding mask is arranged above the semiconductor substrate, and moved in the X-direction and Y-direction for implanting the ions on one chip.
In the doping process of the impurity ions onto the specified regions of the semiconductor substrate, it is required that the kinds of implanted ion, the ion implantation energies and the ion doses be changed. In the conventional ion implantation step, the resist film forming process and the ion implantation process are required to be repeated five to ten times. Such an ion implantation step is very troublesome. The resist film forming process is a wet process, and it is required that the waste fluid is safely and securely treated. For such a problem, the Japanese Patent Opening Gazette No. 003881/2000 improves the ion implantation system disclosed in the above Japanese Patent Opening Gazette No. 288680/1999. In the improved ion implantation system, a stencil mask having openings in correspondence with the specified regions to be implanted, is used instead of the above beam shielding mask. The distance between the stencil mask and the semiconductor substrate is less than about 50 μm.
In an ion implantation system disclosed in U.S. Pat. No. 5,539,203, a PF ion source and a CS sputtering ion source are connected to a switching magnet. The switching magnet is used not only to select one of the two ion sources but also to select a desired kind of ion beam from the selected ion source. The ion beam thus selected by the switching magnet is focused by an electrostatic lens.
At the end, a target chamber and a PIXE chamber are arranged. This patent is directed to a low-energy (0 to 100 keV) or high energy (1 to 4 MeV) single ion implantation system in which single ions are extracted from a focused ion beam or micro-ion beam by beam chopping.